The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device which can realize a reduction in gate-induced drain leakage (GIDL) and a method for manufacturing the same.
As the design rule for achieving more highly integrated semiconductor devices continues to demand decreases the critical dimensions, a problem can arise with regards to unwanted short channel effects across these resultant diminished channel lengths of the highly integrated transistors. Doping concentrations of a source region and a drain region may also need to be increased to enhance the electric fields which can also cause unwanted increases in junction leakage current. Due to these constraints, it is becoming more and more difficult to achieve an appropriate threshold voltage needed in these highly integrated transistor semiconductor devices that are configured to have a planar channel structure. Therefore, limitations necessarily exist in improving refresh characteristics of these highly integrated planar transistor semiconductor devices.
In order to address these problems, a recess gate in which a channel length is effectively increased which results in realizing a suppression of the short channel effect has been proposed and studied in the art. However, since the recess gate is formed so that a gate electrode projects outwardly from a semiconductor substrate, it then becomes more difficult to conduct subsequent processes such as conducting contact plug forming processes and planarization processes without compromising the integrity of the outwardly projecting recess gate.
Under these circumstances, a buried gate in which a gate electrode is formed within the interior of semiconductor substrate has been proposed. In the buried gate configuration, the gate electrode is formed in the semiconductor substrate, and as a result subsequent processes such as contact plug forming processes and planarization processes can be more easily performed without compromising the structural integrity of the buried gate. Furthermore, since the buried gate electrode does not contact a bit line, then advantages can be realized such as decreasing the parasitic capacitance.
When forming the buried gate, a metallic material is mainly used as a gate electrode material. In this regard, since the metallic material has a work function relatively higher than a polysilicon layer, then the gate-induced drain leakage (GIDL) current is prone to increasing. The GIDL current further increases where the gate electrode adjoins a source region and a drain region. Due to this fact, in the conventional art, as leakage current increases, a data retention time decreases, whereby the characteristics and the reliability of a semiconductor device are likely to be compromised.